1. Field of the Invention
The present invention relates generally to methods for forming patterned layers within microelectronic fabrications. More particularly, the present invention relates to methods for forming, with enhanced critical dimension (CD) control, patterned layers within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and microelectronic device and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly important within the art of microelectronic fabrication to monitor and control the critical dimension (CD) of microelectronic devices and patterned microelectronic layers when fabricating microelectronic fabrications. In particular, enhanced critical dimension (CD) control is significant when forming microelectronic devices and patterned microelectronic layers when fabricating microelectronic fabrications since enhanced critical dimension (CD) control typically provides microelectronic fabrications fabricated with enhanced functionality, enhanced reliability and/or enhanced yield.
While enhanced critical dimension (CD) control is thus desirable in the art of microelectronic fabrication when forming microelectronic devices and patterned microelectronic layers within microelectronic fabrications, enhanced critical dimension (CD) control is nonetheless not obtained entirely without problems in the art of microelectronic fabrication when forming microelectronic devices and patterned microelectronic conductor layers within microelectronic fabrications. In that regard, it is often difficult to provide within microelectronic fabrications microelectronic devices and patterned microelectronic layers with enhanced critical dimension (CD) control insofar as there often occurs when forming a microelectronic device or a patterned microelectronic layer within a microelectronic fabrication multiple interrelated parameters which affect the critical dimension (CD) of the microelectronic device or the patterned microelectronic layer within the microelectronic fabrication.
It is thus towards the goal of forming within the art of microelectronic fabrication patterned microelectronic layers, such as but not limited to patterned microelectronic layers which may be formed within microelectronic devices, with enhanced critical dimension (CD) control, that the present invention is directed.
Various methods have been disclosed in the art of microelectronic fabrication for monitoring and/or controlling the critical dimension (CD) of patterned layers formed within microelectronic fabrications.
For example, Corliss, in U.S. Pat. No. 5,427,878 discloses a microelectronic fabrication method which provides for enhanced across-wafer critical dimension (CD) monitoring when fabricating a microelectronic fabrication while employing the microelectronic fabrication method. The microelectronic fabrication method is an optical endpoint detection microelectronic fabrication method which employs in conjunction with a series of critical dimension (CD) test locations spaced across a microelectronic substrate a series of optical detectors positioned corresponding with each of the series of critical dimension (CD) test locations, and where one of the series of critical dimension (CD) test locations is a control critical dimension (CD) test location an optical endpoint detection monitoring of which is employed for controlling processing of the substrate, while the remainder of the series of critical dimension (CD) test locations comprise monitor critical dimension (CD) test locations which provide across-substrate critical dimension (CD) information when processing the substrate while employing the microelectronic fabrication method.
In addition, Liu et al, in U.S. Pat. No. 5,637,186, disclose a monitor test site pattern, and a method which employs the monitor test site pattern when monitoring a microelectronic device critical dimension (CD) when fabricating a microelectronic fabrication while employing the monitor test site pattern, where the monitor test site pattern and the method which employs the monitor testsite pattern provide enhanced accuracy when monitoring the microelectronic device critical dimension (CD) when fabricating the microelectronic device while employing the method which employs the monitor test site pattern. To realize the foregoing result, the monitor test site pattern is fabricated employing layers and dimensions which match the configurations and thicknesses of layers and dimensions employed when fabricating functional microelectronic devices and patterned microelectronic layers within the microelectronic fabrication within which is employed the monitor test site pattern.
Further, Krivokapic et al., in U.S. Pat. No. 5,655,110, disclose a method for providing, with enhanced microelectronic fabrication ease and enhanced microelectronic fabrication efficiency, enhanced critical dimension (CD) control when forming within a microelectronic fabrication a microelectronic device or patterned microelectronic layer while employing a microelectronic fabrication method. To realize the foregoing result, the method provides a computer implemented method which among other features: (1) first statistically determines from a plurality of microelectronic fabrication process parameters within the microelectronic fabrication method those microelectronic fabrication process parameters which provide a most prominent contribution to critical dimension (CD) of a microelectronic device or patterned microelectronic layer formed employing the microelectronic fabrication method; and (2) then determines while employing the most prominent process parameters process parameter adjustments which provide for enhanced critical dimension (CD) control of the microelectronic device or patterned microelectronic layer formed while employing the microelectronic fabrication method.
Still further, Koizumi et al., in U.S. Pat. No. 5,773,174, disclose a method for forming from a blanket photoresist layer within a microelectronic fabrication a patterned photoresist layer with enhanced critical dimension (CD) control within the microelectronic fabrication, without employing a light diffraction method when forming from the blanket photoresist layer within the microelectronic fabrication the patterned photoresist layer with the enhanced critical dimension (CD) control within the microelectronic fabrication. In order to realize the foregoing object, the method employs: (1) measurement within a photoexposed blanket photoresist layer within the microelectronic fabrication while employing an atomic force microscopy (AFM) method a latent photoexposed image height within the photoexposed blanket photoresist layer, in conjunction with; (2) correlation with, and control of, a development time when developing from the photoexposed blanket photoresist layer the patterned photoresist layer to provide the patterned photoresist layer with the enhanced critical dimension (CD) control.
Still yet further, Yang, in U.S. Pat. No. 5,913,102, also disclose a method for forming within a microelectronic fabrication a patterned photoresist layer with enhanced critical dimension (CD) control for use when subsequently forming within the microelectronic fabrication a patterned microelectronic layer with enhanced critical dimension (CD) control. To realize the foregoing result, the method employs when forming the patterned photoresist layer from a blanket photoresist layer measurement of a measurement parameter and subsequent control of a control parameter based upon a measured value of the measurement parameter, each of which measurement parameter and control parameter is independently correlated with the patterned photoresist layer critical dimension (CD) to provide when forming the patterned photoresist layer from the blanket photoresist layer the patterned photoresist layer with the enhanced critical dimension (CD) control.
Finally, Toprac et al., in U.S. Pat. No. 5,926,690, also disclose a method for forming within a microelectronic fabrication from a blanket microelectronic layer a patterned microelectronic layer with enhanced critical dimension (CD) control. To realize the foregoing result, the method employs a two step method for forming from a blanket photoresist layer a patterned photoresist etch mask layer for use when etching from the blanket microelectronic layer the patterned microelectronic layer with the enhanced critical dimension (CD) control, where the first step within the two step method provides for an inadequate development of the patterned photoresist layer from the blanket photoresist layer and a second step within the two step method provides for an additional etching of the inadequately developed patterned photoresist layer to provide a fully patterned photoresist layer.
Desirable in the art of microelectronic fabrication are additional methods and materials which may be employed for forming within microelectronic fabrications microelectronic devices and patterned microelectronic layers with enhanced critical dimension control.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a method for forming within a microelectronic fabrication a patterned microelectronic layer.
A second object of the present invention is to provide a method in accord with the first object of the present invention, where the patterned microelectronic layer is formed with enhanced critical dimension (CD) control.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, which method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for forming within a microelectronic fabrication a patterned layer. To practice a first embodiment of the present invention, there is first provided a stack comprising a substrate, where the substrate has formed thereover a blanket target layer, where the blanket target layer in turn has formed thereover a blanket organic anti-reflective coating (ARC) layer, and where the blanket organic anti-reflective coating (ARC) layer in turn has formed thereover a patterned photoresist layer. There is then established for the stack a correlation which interrelates a patterned photoresist layer target linewidth and an oxygen containing species target concentration in a fashion to provide a patterned target layer having a patterned target layer target linewidth within a sequence of: (1) a first plasma etch method for forming from the blanket organic anti-reflective coating (ARC) layer a patterned organic anti-reflective coating (ARC) layer while employing a first etchant gas composition which upon plasma activation provides the oxygen containing species; and (2) a second plasma etch method for forming the blanket target layer the patterned target layer. There is then determined for the patterned photoresist layer a patterned photoresist layer measured linewidth and a deviation of the patterned photoresist layer measured linewidth from the patterned photoresist layer target linewidth. There is then etched, while employing the first plasma etch method, the blanket organic anti-reflective coating (ARC) layer to form the patterned organic anti-reflective coating (ARC) layer, where the oxygen containing species concentration within the first plasma etch method is adjusted within the context of the correlation to compensate for the deviation of the patterned photoresist layer measured linewidth from the patterned photoresist layer target linewidth such that the blanket target layer may be etched while employing the second plasma etch method to form the patterned target layer having a patterned target layer measured linewidth closer to the patterned target layer target linewidth. Finally, there is then etched, while employing the second plasma etch method, the blanket target layer to form the patterned target layer.
A second embodiment of the present invention follows analogously with the first embodiment of the present invention, but: (1) employs in place of the blanket organic anti-reflective coating (ARC) layer a blanket silicon containing dielectric anti-reflective coating (ARC) layer; and (2) employs in place of the oxygen containing species within the first etchant gas composition for etching the blanket organic anti-reflective coating (ARC) layer to form the patterned organic anti-reflective coating (ARC) layer a bromine containing species within the first etchant gas composition for etching the blanket silicon containing dielectric anti-reflective coating (ARC) layer to form a patterned silicon containing dielectric anti-reflective coating (ARC) layer.
The present invention provides a method for forming within a microelectronic fabrication a patterned layer, where the patterned layer is formed with enhanced critical dimension (CD) control. With a first embodiment, the present invention realizes the foregoing objects by employing when fabricating the patterned layer from a blanket target layer formed beneath a blanket organic anti-reflective coating (ARC) layer in turn formed beneath a patterned photoresist layer within a microelectronic fabrication a correlation which interrelates a patterned photoresist layer target linewidth and an oxygen containing species target concentration in a fashion to provide a patterned target layer having a patterned target layer target linewidth within a sequence of: (1) a first plasma etch method for forming from the blanket organic anti-reflective coating (ARC) layer a patterned organic anti-reflective coating (ARC) layer while employing a first etchant gas composition which upon plasma activation provides the oxygen containing species; and (2) a second plasma etch method for forming the blanket target layer the patterned target layer. The correlation may then be employed for compensating for a deviation of a patterned photoresist layer measured linewidth from the patterned photoresist layer target linewidth by adjusting an oxygen containing species concentration within the first plasma etch method from the oxygen containing species target concentration such that a patterned target layer measured linewidth is closer to the patterned target layer target linewidth.
Within a second embodiment of the invention an analogous result is realized by adjusting within the context of an analogous correlation a bromine containing species concentration within a first plasma etch method to compensate for a deviation of the patterned photoresist layer measured linewidth from the patterned photoresist layer target linewidth under circumstances where there is formed beneath the patterned photoresist layer a blanket silicon containing dielectric anti-reflective coating (ARC) layer rather than the blanket organic anti-reflective coating (ARC) layer.
The method of the present invention is readily commercially implemented. The present invention employs methods and materials as are otherwise generally known in the art of microelectronic fabrication, but employed within the context of a specific materials selection, process ordering and process control to provide the present invention. Since it is a process ordering and process control within the context of a materials selection which provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.